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CY7C374i
UltraLogicTM 128-Macrocell Flash CPLD
Features
128 macrocells in eight logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable (ISRTM) Flash technology -- JTAG interface * Bus Hold capabilities on all I/Os and dedicated inputs * No hidden delays * High speed -- fMAX = 125 MHz -- tPD = 10 ns -- tS = 5.5 ns -- tCO = 6.5 ns * Fully PCI compliant * 3.3V or 5.0V I/O operation * Available in 84-pin PLCC, 84-pin CLCC, and 100-pin TQFP packages * Pin compatible with the CY7C373i * * * *
Functional Description
The CY7C374i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370iTM family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C374i is designed to bring the ease of use as well as PCI Local Bus Specification support and high performance of the 22V10 to high-density CPLDs. Like all of the UltraLogicTM FLASH370i devices, the CY7C374i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pin. The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments. The 128 macrocells in the CY7C374i are divided between eight logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator.
CLOCK INPUTS INPUTS 1 INPUT MACROCELL 4 I/O0-I/O7 8 I/Os LOGIC BLOCK 36 16 36 16 36 16 36 16 PIM 4 INPUT/CLOCK MACROCELLS 4 36 16 36 16 36 16 36 16 LOGIC BLOCK 8 I/Os I/O56-I/O63
Logic Block Diagram
A
8 I/Os LOGIC BLOCK
H
LOGIC BLOCK 8 I/Os
I/O8-I/O15
B
8 I/Os LOGIC BLOCK
G
LOGIC BLOCK 8 I/Os
I/O48-I/O55
I/O16-I/O23
C
8 I/Os LOGIC BLOCK
F
LOGIC BLOCK 8 I/Os
I/O40-I/O47
I/O24-I/O31
D
32
E
32
I/O32-I/O39
7C374i-1
Selection Guide
7C374i-125 Maximum Propagation Delay , tPD (ns) Minimum Set-Up, tS (ns) Maximum Clock to Output[1], tCO (ns) Typical Supply Current, ICC (mA)
[1]
7C374i-100 12 6 7 125
7C374i-83 15 8 8 125
7C374i-66 20 10 10 125
7C374iL-66 20 10 10 75
10 5.5 6.5 125
Note: 1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 October 1995 - Revised December 19, 1997
CY7C374i
Pin Configurations
PLCC Top View
I/O 2 I/O 1 I/O 0 VCCIO GND VCCINT ISR EN I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 GND I/O55 I/O54 /SDI I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I 4 GND VCCIO CLK2/I 3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 7C374i-2 I/O34 I/O36 I/O37 I/O39 I/O35 I/O38 GND SDO I/O40 I/O41 I/O42 I/O43 GND I/O44 CLK2 /I3 VCC I/O46 I/O47 I/O45 GND I/O49 I/O48 CLK3 /I4 I/O50 I/O51 I/O54 I/O52 SDI I/O59 I/O56 GND I/O53 I/O60 8 I/O58 9 I/O57 10 I/O55 11 7C374i-3 GND I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O8 I/O9 I/O10 /SCLK I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I 0 VCCIO GND CLK1/I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 L I/O23 I/O25 I/O26 I/O28 SMODE I/O24 I/O27
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O26 /SMODE I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCCIO GND VCCINT I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 /SDO I/O39 GND
PGA Bottom View
I/O31 I/O33 VCC
K
I/O21
GND
I/O30
I2
I/O32
J
I/O20
I/O22
I/O29
VCC
GND
H
I/O18 CLK1 / I1 I/O17
I/O19 I/O16
G
F
CLK0 /I0 I/O14
VCC
E
I/O15
I/O13
D
I/O12
I/O11
C
I/O10 I/O8 SCLK I/O9 GND I/O6 I/O3
I/O1
VCC
ISREN I/O62
B
I/O0
I/O61
A
I/O7 1
I/O5 2
I/O4 3
I/O2 4
VCC 5
GND 6
I/O63 7
2
CY7C374i
Pin Configurations (continued)
TQFP Top View
NC VCCIO VCCINT NC I/O 0 VCCIO GND ISREN I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 GND NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SCLK GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0 /I0 VCCIO N/C GND CLK1 /I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCCIO NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SDI VCCIO I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3 /I4 GND NC VCCIO CLK2 /I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 GND NC
VCCIO
SMODE GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29
CLCC Top View
I/O 2 I/O 1 I/O 0 VCC GND VCC ISREN I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 GND I/O 7 I/O 6 I/O 5 I/O 4 I/O 3
I/O8 I/O9 I/O10 /SCLK I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I 0 VCC GND CLK1/I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O26 /SMODE I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 /SDO I/O39 GND I/O24 I/O25
NC GND VCCINT I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39
VCCIO
I/O30 I/O31 I2
7C374i-2
3
SDO
7C374i-4
GND I/O55 I/O54 /SDI I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I 4 GND VCC CLK2/I 3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40
CY7C374i
Functional Description (continued)
The logic blocks in the FLASH370i architecture are connected with an extremely fast and predictable routing resource--the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. Like all members of the FLASH370i family, the CY7C374i is rich in I/O resources. Every two macrocells in the device feature an associated I/O pin, resulting in 64 I/O pins on the CY7C374i. In addition, there is one dedicated input and four input/clock pins. Finally, the CY7C374i features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used or the type of application, the timing parameters on the CY7C374i remain the same. Logic Block The number of logic blocks distinguishes the members of the FLASH370i family. The CY7C374i includes eight logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. boring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C374i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Programming For an overview of ISR programming, refer to the FLASH370i Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of ISR capabilities, refer to the Cypress application note, "An Introduction to In System Reprogramming with FLASH370i." PCI Compliance The FLASH370i family of CMOS CPLDs are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The simple and predictable timing model of FLASH370i ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without simple and predictable timing, PCI compliance is dependent upon routing and product term distribution. 3.3V or 5.0V I/O Operation The FLASH370i family can be configured to operate in both 3.3V and 5.0V systems. All devices have two sets of VCC pins: one set, VCCINT, for internal operation and input buffers, and another set, VCCIO, for I/O output drivers. VCCINT pins must always be connected to a 5.0V power supply. However, the VCCIO pins may be connected to either a 3.3V or 5.0V power supply, depending on the output requirements. When VCCIO pins are connected to a 5.0V source, the I/O voltage levels are compatible with 5.0V systems. When VCCIO pins are connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay on all output buffers when operating in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is available in commercial and industrial temperature ranges. Bus Hold Capabilities on all I/Os and Dedicated Inputs In addition to ISR capability, a new feature called bus-hold has been added to all FLASH370i I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. Design Tools Development software for the CY7C371i is available from Cypress's Warp2(R), Warp2SimTM, and Warp3(R) software packages. All of these products are based on the IEEE-standard VHDL language. Cypress also actively supports third-party design tools from companies such as Synopsys, Mentor Graphics, Cadence, and Synario. Please refer to third-party tool support for further information.
Product Term Array
The product term array in the FLASH370i logic block includes 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex functions to be implemented in single passes through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370i CPLDs. Note that product term allocation is handled by software and is invisible to the user.
I/O Macrocell
Half of the macrocells on the CY7C374i have I/O pins associated with them. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The I/O macrocell includes a register that can be optionally bypassed, polarity control over the input sum-term, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input.
Buried Macrocell
The buried macrocell is very similar to the I/O macrocell. Again, it includes a register that can be configured as combinatorial, as a D flip-flop, a T flip-flop, or a latch. The clock for this register has the same options as described for the I/O macrocell. One difference on the buried macrocell is the addition of input register capability. The user can program the buried macrocell to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neigh4
CY7C374i
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V DC Program Voltage .....................................................12.5V Output Current into Outputs......................................... 16 mA
Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC VCCINT 5V .25V VCCIO 5V .25V OR 3.3V .3V 5V .5V OR 3.3V .3V
Industrial
-40C to +85C
5V .5V
Military[2]
-55C to +125C
5V .5V
Electrical Characteristics Over the Operating Range[3, 4]
Parameter VOH VOHZ VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output HIGH Voltage with Output Disabled[9] Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[8, 9] Power Supply Current VCC = Min. VCC = Max. VCC = Min. Test Conditions IOH = -3.2 mA (Com'l/Ind) IOH = -2.0 mA (Mil) IOH = 0 A (Com'l/Ind)
[5, 6] [5]
Min. 2.4
Typ.
Max.
Unit V V
4.0 3.6 0.5
[7]
V V V V V V A A A mA mA mA mA A A
IOH = -50 A (Com'l/Ind)[5, 6] IOL = 16 mA (Com'l/Ind) IOL = 12 mA (Mil) Guaranteed Input Logical HIGH voltage for all inputs VI = Internal GND, VI = VCC VCC = Max., VO = GND or VO = VCC, Output Disabled VCC = Max., VO = 3.3V, Output Disabled VCC = Max., VOUT = 0.5V VCC = Max., IOUT = 0 mA, f = 1 MHz, VIN = GND, VCC
[10] [6] [5]
2.0 -0.5 -10 -50 0 -30 -70
7.0 0.8 +10 +50 -125 -160 125 75 125 200 125 250
Guaranteed Input Logical LOW voltage for all inputs[7]
Com'l/Ind. Com'l "L" -66 Military +75 -75
IBHL IBHH IBHLO IBHHO
Input Bus Hold LOW Sustaining Current Input Bus Hold HIGH Sustaining Current Input Bus Hold LOW Overdrive Current Input Bus Hold HIGH Overdrive Current
VCC = Min., VIL = 0.8V VCC = Min., VIH = 2.0V VCC = Max. VCC = Max.
+500 -500
A A
Notes: 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT. 5. IOH = -2 mA, I OL = 2 mA for SDO. 6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note "Understanding Bus Hold" for additional information. 7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 9. Tested initially and after any design or process changes that may affect these parameters. 10. Measured with 16-bit counter programmed into each logic block.
5
CY7C374i
Capacitance[9]
Parameter CI/O[11, 12] CCLK Description Input Capacitance Clock Signal Capacitance Test Conditions VIN = 5.0V at f=1 MHz VIN = 5.0V at f = 1 MHz 5 Min. Max. 8 12 Unit pF pF
Inductance[9]
Parameter L Description Maximum Pin Inductance Test Conditions VIN = 5.0V at f = 1 MHz 100-PinTQFP 8 84-Lead PLCC 8 84-Lead CLCC 5 Unit nH
Endurance Characteristics[9]
Parameter N Description Maximum Reprogramming Cycles Test Conditions Normal Programming Conditions Max. 100 Unit Cycles
AC Test Loads and Waveforms
238 (COM'L) 319 (MIL) 5V OUTPUT 35 pF INCLUDING JIG AND SCOPE 170 (COM'L) 236 (MIL) 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 170 (COM'L) 236 (MIL) 238 (COM'L) 319 (MIL) ALL INPUT PULSES 3.0V 90% GND <2ns 10% 90% 10% <2ns
(a)
Equivalent to: THEVENIN EQUIVALENT 99 (COM'L) 136 (MIL) 2.08V (COM'L) 2.13V (MIL)
(b)
(c)
7C374i-5
7C374i-6
OUTPUT
Parameter[13] tER(-)
VX 1.5V VOH
Output Waveform Measurement Level
-0.5V tER(+) 2.6V -0.5V VOH tEA(+) 1.5V -0.5V VX tEA(-) Vthc VX -0.5V
Notes: 11. CI/O for the CLCC package are 12 pF Max 12. CI/O for dedicated Inputs, and for I/O pins with JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max. 13. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
VX VX
VOH
VOH
6
CY7C374i
Switching Characteristics Over the Operating Range[14]
7C374i-125 Parameter tPD tPDL tPDLL tEA tER tWL tWH tIS tIH tICO tICOL Description Input to Combinatorial Output[1] Input to Output Through Transparent Input or Output Latch[1] Input to Output Through Transparent Input and Output Latches[1] Input to Output Enable[1] Input to Output Disable Clock or Latch Enable Input LOW Time[9] Clock or Latch Enable Input HIGH Time[9] Input Register or Latch Set-Up Time Input Register or Latch Hold Time Input Register Clock or Latch Enable to Combinatorial Output[1] Input Register Clock or Latch Enable to Output Through Transparent Output Latch [1] Clock or Latch Enable to Output[1] Set-Up Time from Input to Clock or Latch Enable Register or Latch Data Hold Time Output Clock or Latch Enable to Output Delay (Through Memory Array) [1] Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable Maximum Frequency with Internal Feedback (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[9] Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH)) Output Data Stable from Output Clock Minus Input Register Hold Time for 7C37x[9, 15] Input Register Clock to Output Register Clock Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) 8 10 5.5 0 14 10 12 3 3 2 2 14 16 Min. Max. 10 13 15 14 14 3 3 2 2 16 18 Combinatorial Mode Parameters 12 15 16 16 16 4 4 3 3 19 21 15 18 19 19 19 5 5 4 4 24 26 20 22 24 24 24 ns ns ns ns ns ns ns ns ns ns ns 7C374i-100 Min. Max. 7C374i-83 Min. Max. 7C374i-66 7C374iL-66 Min. Max. Unit
Input Registered/Latched Mode Parameters
Output Registered/Latched Mode Parameters tCO tS tH tCO2 tSCS tSL 6.5 6 0 16 12 15 7 8 0 19 15 20 8 10 0 24 10 ns ns ns ns ns ns
tHL
0
0
0
0
ns
fMAX1 fMAX2
125 158.3
100 143
83 125
66 100
MHz MHz
fMAX3 tOH-tIH 37x tICS fMAX4
83.3 0
76.9 0
67.5 0
50 0
MHz ns
Pipelined Mode Parameters 8 125 10 100 12 83.3 15 66.6 ns MHz
Notes: 14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.
7
CY7C374i
Switching Characteristics Over the Operating Range[14] (continued)
7C374i-125 Parameter Reset/Preset Parameters tRW tRR tRO tPW tPR tPO fTAP t3.3IO Asynchronous Reset Width[9] Asynchronous Reset Recovery Time[9] Asynchronous Reset to Output Asynchronous Preset Width[9] Asynchronous Preset Recovery Time Asynchronous Preset to Output[1] Tap Controller Frequency 3.3V I/O mode timing adder 500 1
[9] [1]
7C374i-100 Min. 12 14 Max.
7C374i-83 Min. 15 17 Max.
7C374i-66 7C374iL-66 Min. 20 22 Max. Unit ns ns 26 20 22 ns ns ns 26 500 ns kHz 1 ns
Description
Min. 10 12
Max.
16 10 12 16 500 12 14
18 15 17 18 500 1
21
21
Tap Controller Parameter 3.3V I/O Mode Parameters 1
Switching Waveforms
Combinatorial Output
INPUT tPD COMBINATORIAL OUTPUT
7C374i-7
Registered Output
INPUT tS CLOCK tCO REGISTERED OUTPUT tWH tWL tH
CLOCK
7C374i-8
Latched Output
INPUT tS LATCH ENABLE tPDL LATCHED OUTPUT
7C374i-9
tH
tCO
8
CY7C374i
Switching Waveforms (continued)
Registered Input
REGISTERED INPUT tIS INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tWH CLOCK tWL tIH
7C374i-10
Latched Input
LATCHED INPUT tIS LATCH ENABLE tPDL COMBINATORIAL OUTPUT tICO tIH
tWH LATCH ENABLE
tWL
7C374i-11
Latched Input and Output
LATCHED INPUT
tPDLL LATCHED OUTPUT tICOL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tWH LATCH ENABLE
7C374i-12
tSL tHL
tWL
9
CY7C374i
Switching Waveforms (continued)
Asynchronous Reset
tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK
7C374i-13
Asynchronous Preset
tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK
7C374i-14
Output Enable/Disable
INPUT tER OUTPUTS
7C374i-16
tEA
10
CY7C374i
Ordering Information
Speed (MHz) 125 100 83 Ordering Code CY7C374i-125AC CY7C374i-125JC CY7C374i-100AC CY7C374i-100JC CY7C374i-83AC CY7C374i-83JC CY7C374i-83AI CY7C374i-83JI CY7C374i-83GMB CY7C374i-83YMB 66 CY7C374i-66AC CY7C374I-66JC CY7C374i-66AI CY7C374i-66JI CY7C374i-66GMB CY7C374i-66YMB CY7C374iL-66AC CY7C374iL-66JC Package Name A100 J83 A100 J83 A100 J83 A100 J83 G84 Y84 A100 J83 A100 J83 G84 Y84 A100 J83 Package Type 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 84-Pin Ceramic Pin Grid Array 84-Pin Ceramic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 84-Pin Ceramic Pin Grid Array 84-Pin Ceramic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier Commercial Military Industrial Commercial Military Industrial Commercial Commercial Operating Range Commercial
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC1 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter tPD tPDL tPDLL tCO tICO tICOL tS tSL tH tHL tIS tIH tICS tEA tER Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
Document #: 38-00496-C ISR, UltraLogic, FLASH370, FLASH370i, and Warp2Sim are trademarks of Cypress Semiconductor Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
11
CY7C374i
Package Diagrams
100-Pin Thin Quad Flat Pack A100
84-Pin Grid Array (Cavity Up) G84
12
CY7C374i
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
84-Pin Ceramic Leaded Chip Carrier Y84
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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